Integrated circuit fabrication often includes forming one or more isolation regions to define one or more active regions on a silicon or other substrate of a semiconductor structure. One way to form an isolation region is to form one or more trenches in the substrate using one or more etching processes while masking the substrate over what is to be the active region. As an example, this process may be referred to as shallow trench isolation (STI). Subsequent to formation, a liner oxide layer may be formed in the trenches and the trenches may be filled with a fill oxide to form the isolation regions. The etching processes for forming the isolation regions may lead to problems that may degrade transistor performance. These problems may include a step-height problem associated with the STI process (i.e. the “1/w effect”), stress created by the liner oxide used during the STI process, strained channels underlying a gate formed on the semiconductor structure, or other problems.
Furthermore, the substrate and active regions may be doped with a dopant material such as boron using an implant process. An anneal process may be used to activate the dopant material, which may cause undesirable levels of diffusion of the dopant material in the substrate. The combined implant and anneal process for doping the active region may result in a doping gradient (i.e. the variation of dopant concentration with depth) that is not as steep as desired as well as other problems.
Integrated circuit fabrication may also include forming a transistor on an active region of the semiconductor structure. One way to form a transistor on the surface of the active region is to implant dopant material into portions of the active region to form a source and drain of the transistor. A gate may be formed on a pad layer on the surface of the active region over a channel formed between the source and the drain. Using previous techniques to form the transistor may degrade or otherwise limit performance of the transistor as a result of diffusion of the dopant material during an anneal process for activating the dopant material. Furthermore, the geometry of transistors formed according to previous techniques may limit or otherwise degrade transistor performance.